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| Preliminary 84 Link Inverse Multiplexer for ATM (IMA) / UNI PHY FEATURES IMA ATM OVER FRACTIONAL T1/E1 * Supports up to 32 ATM over Fractional T1/E1 UNIs over the clock/data interface, compliant with the ATM Forum AF-PHY-0130.00 specification. PM7341 S/UNI(R)-IMA-84 * Supports up to 84 T1 or 63 E1 links and up to 42 IMA groups with 1 to 32 links/group. LINE INTERFACE * Link and Group State Machines * Supports a 19.44 MHz Scalable Bandimplemented on-chip requiring no real width Interconnect (SBI) bus interface for time software in the data path. seamless interconnect to the PM8315 * Fully compliant with the ATM Forum TEMUX and PM8316 TEMUX-84. Inverse Multiplexer for ATM (IMA) * SBI supports three Synchronous 1.1 specification and backward Payload Envelopes (SPE) where each compatible to IMA 1.0. SPE can carry up to 28 T1s, 21 E1s, or * Supports both independent transmit one unchannelized DS3 stream. clock (ITC) and common transmit clock * Supports up to 32 T1, E1, G.SHDSL or (CTC) modes. unchannelized links via 2-pin line * Supports all IMA Group Symmetry interfaces. modes: Symmetric/Asymmetric configuration and operation. UTOPIA / ANY-PHY INTERFACE * Differential delay tolerance of 279 ms * Supports 8- and 16-bit UTOPIA L2 and (for T1 links) and 226 ms (for E1 links). Any-PHY cell interfaces at clock rates * Performs IMA differential delay up to 52 MHz. calculation and synchronization. * Any-PHY transmit slave appears as an * Provides programmable limit on 84 port multi-PHY. The PHY-ID of allowable differential delay and each cell is identified using in-band minimum number of links per group. addressing. * Performs ICP and stuff-cell insertion and removal. BLOCK DIAGRAM * Supports IMA frame length (M) equal to 32, 64, 128, or 256. * Provides IMA layer statistic counts and alarms for support of SBI Add Bus I/F IMA Performance and Failure AC1FP ADATA[7:0] DLL Alarm Monitoring and MIB ADP Null APL support. INSBI Framer AV5 (SDFR84) AJUST_REQ * Provides per link counters for AACTIVE 84-chan ADETECT statistics and performance TC Layer x 7 cell (TTTC84) FIFO 32 Clk/Data monitoring. (MCFD) REFCLK SYSCLK OE RSTB * Any-PHY receive slave appears as a single device. The PHY-ID of each cell is identified using in-band addressing. * UTOPIA L2 transmit and receive slave appears as a 31-port multi-PHY. * UTOPIA L2 receive slave can also appear as a single port with the logical port provided as a prepend. LOOPBACK AND DIAGNOSTICS * Supports UTOPIA Side Loopback. * Supports Line Side Loopback. * Supports per group ICP cell trace capability. SOFTWARE * The S/UNI-IMA device driver, written in ANSI C, provides a well-defined API and low level utility functions for diagnostics and debugging purposes * Software wrappers are used for RTOSrelated functions making the S/UNIIMA device driver portable to any Real Time Operating System (RTOS) environment. D[15:0] A[10:1] ALE WRB RDB CSB INTB TCK TMS TDI TRSTB TDO MicroProcess I/F JTAG Tx Slave ATM I/F Tx IMA Processor (TIMA) 84-chan x 3 cell FIFO Any-PHY/ UTOPIA Tx Slave (TXAPS) UNI * Supports up to 84/63 ATM over T1/E1 UNIs or 3 ATM over DS3 UNIs. * Each T1/E1 link is software configurable as either a UNI or part of an IMA group. * Performs receive cell Header Error Check (HEC) checking and transmit cell HEC generation. * Optionally supports receive cell payload unscrambling and transmit cell payload scrambling. * Provides TC layer statistics counts and alarms for MIB support. TSCLK[31:0] TSDATA[31:0] CTSCLK TCAS IDCC TCLK TPA TENB TADR[10:0] TCSB TSOP TSX TDAT[15:0] TPRTY Internal Bus IDCC 32 Clk/Data Rx IMA Protocol Processor (RIPP) Rx Slave ATM I/F RSCLK[31:0] RSDATA[31:0] SBI Drop Bus I/F RCAS TC Layer (RTTC84) DeFramer (SDDF84) DC1FP DDATA[7:0] DDP DPL DV5 84-chan x 2 cell FIFO Rx IMA Data Processor (RDAT) Cell Writer Cell Reader 31 chan 4 cell FIFO Any-PHY/ UTOPIA Rx Slave (RXAPS) EXSBI RCLK RPA RENB RADR[4:0] RCSB RSOP RSX RDAT[15:0] RPRTY Memory Interface (MEMI) PMC-2001522 (p4) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE CBCSB CBRASB CBCASB CBWEB CBA[11:0] CBBS[1:0] CBDQM CBDQ[15:0] (c) Copyright PMC-Sierra, Inc. 2001 Preliminary PM7341 S/UNI(R)-IMA-84 84 Link Inverse Multiplexer for ATM (IMA) / UNI PHY GENERAL * 16-bit interface for 1M x 16 or 4M x 16 SDRAM, depending on the differential delay tolerance. * Provides a 16-bit microprocessor interface for configuration, statistics gathering and Link and Unit Management. * Provides a standard 5-pin P1149 JTAG port. * Low-power 1.8 V CMOS with TTL-compatible I/O. * 416-pin plastic ball grid array (PBGA) package. APPLICATIONS * Multiservice Switches. * Optical Access Switches. * Wireless Basestation Controllers. TYPICAL APPLICATIONS ATM MULTISERVICE SWITCH TelecomBus SBI Any-PHY (Packet) UTOPIA L2/ Any-PHY (Cell) PM8316 TEMUX-84 PM7385 FREEDM84A672 Packet/Cell Internetworking Function PM8316 TEMUX-84 PM5313 SPECTRA622 PM8316 TEMUX-84 PM7341 S/UNI-IMA84 Any-PHY APPI PM7326 S/UNI-APEX OC-12 PM73122 PM73122 AAL1gatorPM73122 AAL1gator32 AAL1gator32 32 PM7324 S/UNIATLAS PM8316 TEMUX-84 SBI to H-MVIP VoATM DSP WIRELESS BASESTATION CONTROLLER TelecomBus PM5342 SPECTRA155 OR PM5342 PM5342 SPECTRASPECTRADS3 LIUs 155 155 PM8316 TEMUX-84 PM7341 S/UNI-IMA84 SBI UTOPIA L2 / Any-PHY PM7329 S/UNI-APEX1K800 PM7328 S/UNI-ATLAS1K800 Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: +1.604.415.6000 Fax: +1.604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-2001522 (p4) (c) Copyright PMC-Sierra, Inc. 2001. All rights reserved. October 2001. S/UNI is a registered trademark of PMC-Sierra, Inc. SBI, AAL1gator, FREEDM, SPECTRA, AAL1gator, COMET-QUAD, and Any-PHY are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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